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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC14536B Programmable Timer The MC14536B programmable timer is a 24-stage binary ripple counter with 16 stages selectable by a binary code. Provisions for an on-chip RC oscillator or an external clock are provided. An on-chip monostable circuit incorporating a pulse-type output has been included. By selecting the appropriate counter stage in conjunction with the appropriate input clock frequency, a variety of timing can be achieved. * 24 Flip-Flop Stages -- Will Count From 20 to 224 * * * * * * * Last 16 Stages Selectable By Four-Bit Select Code 8-Bypass Input Allows Bypassing of First Eight Stages Set and Reset Inputs Clock Inhibit and Oscillator Inhibit Inputs On-Chip RC Oscillator Provisions On-Chip Monostable Output Provisions Clock Conditioning Circuit Permits Operation With Very Long Rise and Fall Times * Test Mode Allows Fast Test Sequence * Supply Voltage Range = 3.0 Vdc to 18 Vdc * Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol VDD Parameter DC Supply Voltage L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 DW SUFFIX SOIC CASE 751G ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBDW Plastic Ceramic SOIC TA = - 55 to 125C for all packages. IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII Value Unit V V - 0.5 to + 18.0 10 500 - 65 to + 150 Vin, Vout Iin, Iout PD Tstg Input or Output Voltage (DC or Transient) - 0.5 to VDD + 0.5 Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature mA mW _C TL Lead Temperature (8-Second Soldering) 260 _C * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C BLOCK DIAGRAM CLOCK INH. 7 OSC. INHIBIT 14 STAGES 1 THRU 8 4 OUT1 5 OUT2 VDD = PIN 16 VSS = PIN 8 STAGES 9 THRU 24 QQQQQQQQQQQQQQQQ 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 A9 B 10 C 11 D 12 RESET SET 8 BYPASS 2 16 IN1 3 DECODER MONO-IN 15 MONOSTABLE MULTIVIBRATOR 13 DECODE OUT REV 3 1/94 (c)MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995 MC14536B 1 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source Pins 4 & 5 5.0 5.0 10 15 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 - 1.2 - 0.25 - 0.62 - 1.8 - 3.0 - 0.64 - 1.6 - 4.2 0.64 1.6 4.2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.1 -- 5.0 10 20 - 1.0 - 0.25 - 0.5 - 1.5 - 2.4 - 0.51 - 1.3 - 3.4 0.51 1.3 3.4 -- -- -- -- -- - 1.7 - 0.36 - 0.9 - 3.5 - 4.2 - 0.88 - 2.25 - 8.8 0.88 2.25 8.8 0.00001 5.0 0.010 0.020 0.030 -- -- -- -- -- -- -- -- -- -- -- 0.1 7.5 5.0 10 20 - 0.7 - 0.14 - 0.35 - 1.1 - 1.7 - 0.36 - 0.9 - 2.4 0.36 0.9 2.4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.0 -- 150 300 600 mAdc 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -- -- -- 3.5 7.0 11 -- -- -- mAdc Min -- -- -- - 55_C 25_C 125_C Max Min -- -- -- Typ # 0 0 0 Max Min -- -- -- Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 0.05 0.05 0.05 -- -- -- 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) VIL -- -- -- -- -- -- 2.25 4.50 6.75 -- -- -- VOH 4.95 9.95 14.95 4.95 9.95 14.95 5.0 10 15 4.95 9.95 14.95 Vdc Vdc Source Pin 13 Sink mAdc Iin Cin IDD Adc pF Adc IT IT = (1.50 A/kHz) f + IDD IT = (2.30 A/kHz) f + IDD IT = (3.55 A/kHz) f + IDD Adc #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.003. MC14536B 2 MOTOROLA CMOS LOGIC DATA IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C) Characteristic Output Rise and Fall Time (Pin 13) tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns Propagation Delay Time Clock to Q1, 8-Bypass (Pin 6) High tPLH, tPHL = (1.7 ns/pF) CL + 1715 ns tPLH, tPHL = (0.66 ns/pF) CL + 617 ns tPLH, tPHL = (0.5 ns/pF) CL + 425 ns Clock to Q1, 8-Bypass (Pin 6) Low tPLH, tPHL = (1.7 ns/pF) CL + 3715 ns tPLH, tPHL = (0.66 ns/pF) CL + 1467 ns tPLH, tPHL = (0.5 ns/pF) CL + 1075 ns Clock to Q16 tPHL, tPLH = (1.7 ns/pF) CL + 6915 ns tPHL, tPLH = (0.66 ns/pF) CL + 2967 ns tPHL, tPLH = (0.5 ns/pF) CL + 2175 ns Reset to Qn tPHL = (1.7 ns/pF) CL + 1415 ns tPHL = (0.66 ns/pF) CL + 567 ns tPHL = (0.5 ns/pF) CL + 425 ns Clock Pulse Width Symbol tTLH, tTHL VDD 5.0 10 15 Min -- -- -- Typ # 100 50 40 Max 200 100 80 Unit ns tPLH, tPHL 5.0 10 15 tPLH, tPHL 5.0 10 15 5.0 10 15 5.0 10 15 tWH 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 1000 400 300 -- -- -- -- -- -- -- -- -- -- -- -- 600 200 170 -- -- -- 1800 650 450 3.8 1.5 1.1 7.0 3.0 2.2 1500 600 450 300 100 85 1.2 3.0 5.0 No Limit 500 200 150 -- -- -- ns 3600 1300 1000 s 7.6 3.0 2.3 s 14 6.0 4.5 ns 3000 1200 900 -- -- -- 0.4 1.5 2.0 ns ns tPLH, tPHL tPHL Clock Pulse Frequency (50% Duty Cycle) Clock Rise and Fall Time fcl MHz tTLH, tTHL tWH -- Reset Pulse Width * The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. PIN ASSIGNMENT SET RESET IN 1 OUT 1 OUT 2 8-BYPASS CLOCK INH VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD MONO IN OSC INH DECODE D C B A MOTOROLA CMOS LOGIC DATA MC14536B 3 PIN DESCRIPTIONS INPUTS SET (Pin 1) -- A high on Set asynchronously forces Decode Out to a high level. This is accomplished by setting an output conditioning latch to a high level while at the same time resetting the 24 flip-flop stages. After Set goes low (inactive), the occurrence of the first negative clock transition on IN1 causes Decode Out to go low. The counter's flip-flop stages begin counting on the second negative clock transition of IN1. When Set is high, the on-chip RC oscillator is disabled. This allows for very low-power standby operation. RESET (Pin 2) -- A high on Reset asynchronously forces Decode Out to a low level; all 24 flip-flop stages are also reset to a low level. Like the Set input, Reset disables the on-chip RC oscillator for standby operation. IN1 (Pin 3) -- The device's internal counters advance on the negative-going edge of this input. IN1 may be used as an external clock input or used in conjunction with OUT 1 and OUT 2 to form an RC oscillator. When an external clock is used, both OUT 1 and OUT 2 may be left unconnected or used to drive 1 LSTTL or several CMOS loads. 8-BYPASS (Pin 6) -- A high on this input causes the first 8 flip-flop stages to be bypassed. This device essentially becomes a 16-stage counter with all 16 stages selectable. Selection is accomplished by the A, B, C, and D inputs. (See the truth tables.) CLOCK INHIBIT (Pin 7) -- A high on this input disconnects the first counter stage from the clocking source. This holds the present count and inhibits further counting. However, the clocking source may continue to run. Therefore, when Clock Inhibit is brought low, no oscillator start-up time is required. When Clock Inhibit is low, the counter will start counting on the occurrence of the first negative edge of the clocking source at IN1. OSC INHIBIT (Pin 14) -- A high level on this pin stops the RC oscillator which allows for very low-power standby operation. May also be used, in conjunction with an external clock, with essentially the same results as the Clock Inhibit input. MONO-IN (Pin 15) -- Used as the timing pin for the on- chip monostable multivibrator. If the Mono-In input is connected to V SS , the monostable circuit is disabled, and Decode Out is directly connected to the selected Q output. The monostable circuit is enabled if a resistor is connected between Mono-In and V DD. This resistor and the device's internal capacitance will determine the minimum output pulse widths. With the addition of an external capacitor to V SS, the pulse width range may be extended. For reliable operation the resistor value should be limited to the range of 5 k to 100 k and the capacitor value should be limited to a maximum of 1000 pf. (See figures 3, 4, 5, and 10). A, B, C, D (Pins 9, 10, 11, 12) -- These inputs select the flip-flop stage to be connected to Decode Out. (See the truth tables.) OUTPUTS OUT1, OUT2 (Pin 4, 5) -- Outputs used in conjunction with IN1 to form an RC oscillator. These outputs are buffered and may be used for 20 frequency division of an external clock. DECODE OUT (Pin 13) -- Output function depends on configuration. When the monostable circuit is disabled, this output is a 50% duty cycle square wave during free run. TEST MODE The test mode configuration divides the 24 flip-flop stages into three 8-stage sections to facilitate a fast test sequence. The test mode is enabled when 8-Bypass, Set and Reset are at a high level. (See Figure 8.) MC14536B 4 MOTOROLA CMOS LOGIC DATA TRUTH TABLES Input 8-Bypass 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Input 8-Bypass 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Stage Selected for Decode Out 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Stage Selected for Decode Out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FUNCTION TABLE Clock Inh 0 0 0 0 1 0 0 0 OSC Inh 0 0 0 0 0 1 X 0 0 -- 0 0 1 1 -- 1 1 Decode Out No Change Advance to next state 1 0 No Change No Change No Change Advance to next state In1 Set 0 0 Reset 0 0 0 1 0 0 0 0 Out 1 Out 2 X X X X 0 1 1 0 0 0 0 0 X = Don't Care MOTOROLA CMOS LOGIC DATA MC14536B 5 MC14536B 6 RESET 2 8-BYPASS 6 T1 8 4 OUT 1 C Q En R SET 1 7 CLOCK INHIBIT DECODER OUT 13 S A B C D 9 10 11 12 OUT 2 5 STAGES 2 THRU 7 T9 STAGES 10 THRU 15 16 17 STAGES 18 THRU 23 24 OSC INHIBIT 14 3 IN1 LOGIC DIAGRAM DECODER MOTOROLA CMOS LOGIC DATA 15 MONO-IN VDD = PIN 16 VSS = PIN 8 TYPICAL RC OSCILLATOR CHARACTERISTICS (For Circuit Diagram See Figure 11 In Application) 8.0 VDD = 15 V FREQUENCY DEVIATION (%) 4.0 0 10 V - 4.0 - 8.0 - 12 - 16 - 55 - 25 * Device Only. RTC = 56 k, C = 1000 pF RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25C RS = 120 k, f = 7.8 kHz @ VDD = 10 V, TA = 25C 100 50 f, OSCILLATOR FREQUENCY (kHz) 20 10 5.0 2.0 1.0 0.5 0.2 0.1 1.0 k 0.0001 10 k 100 k RTC, RESISTANCE (OHMS) 0.001 0.01 C, CAPACITANCE (F) 1.0 M 0.1 f AS A FUNCTION OF C (RTC = 56 k) (RS = 120 k) VDD = 10 V f AS A FUNCTION OF RTC (C = 1000 pF) (RS 2RTC) 5.0 V 0 25 50 75 TA, AMBIENT TEMPERATURE (C)* 100 125 Figure 1. RC Oscillator Stability Figure 2. RC Oscillator Frequency as a Function of RTC and C MONOSTABLE CHARACTERISTICS (For Circuit Diagram See Figure 10 In Application) 100 FORMULA FOR CALCULATING tW IN MICROSECONDS IS AS FOLLOWS: tW = 0.00247 RX * CX 0.85 WHERE R IS IN k, CX IN pF. 100 FORMULA FOR CALCULATING tW IN MICROSECONDS IS AS FOLLOWS: tW = 0.00247 RX * CX 0.85 WHERE R IS IN k, CX IN pF. t W, PULSE WIDTH ( s) t W, PULSE WIDTH ( s) 10 10 RX = 100 k 50 k 1.0 10 k 5 k TA = 25C VDD = 5 V 0.1 1.0 10 100 CX, EXTERNAL CAPACITANCE (pF) 1000 RX = 100 k 50 k 1.0 10 k 5 k 0.1 1.0 10 100 CX, EXTERNAL CAPACITANCE (pF) 1000 TA = 25C VDD = 10 V Figure 3. Typical CX versus Pulse Width @ VDD = 5.0 V 100 FORMULA FOR CALCULATING tW IN MICROSECONDS IS AS FOLLOWS: tW = 0.00247 RX * CX 0.85 WHERE R IS IN k, CX IN pF. Figure 4. Typical CX versus Pulse Width @ VDD = 10 V t W, PULSE WIDTH ( s) 10 RX = 100 k 50 k 1.0 10 k 5 k 0.1 1.0 10 100 CX, EXTERNAL CAPACITANCE (pF) 1000 TA = 25C VDD = 15 V Figure 5. Typical CX versus Pulse Width @ VDD = 15 V MOTOROLA CMOS LOGIC DATA MC14536B 7 VDD 500 F ID 0.01 F CERAMIC 20 ns 50% tWL OUT tPLH 90% 10% tTLH tTHL tWH 50% tPHL PULSE GENERATOR SET RESET OUT 1 8-BYPASS IN1 C INH MONO IN OUT 2 OSC INH A B C D 20 ns CL VDD SET OUT 1 RESET 8-BYPASS IN1 C INH MONO IN OUT 2 OSC INH A B C DECODE OUT D VSS IN1 CL PULSE GENERATOR DECODE OUT VSS CL 20 ns 90% 50% 10% 50% DUTY CYCLE 20 ns CL Figure 6. Power Dissipation Test Circuit and Waveform Figure 7. Switching Time Test Circuit and Waveforms FUNCTIONAL TEST SEQUENCE Test function (Figure 8) has been included for the reduction of test time required to exercise all 24 counter stages. This test function divides the counter into three 8-stage sections and 255 counts are loaded in each of the 8-stage sections in parallel. All flip-flops are now at a "1". The counter is now returned to the normal 24-stages in series configuration. One more pulse is entered into In1 which will cause the counter to ripple from an all "1" state to an all "0" state. PULSE GENERATOR VDD SET RESET OUT 1 8-BYPASS IN1 C INH MONO IN OUT 2 OSC INH A B C D DECODE OUT VSS Figure 8. Functional Test Circuit FUNCTIONAL TEST SEQUENCE Inputs In1 1 1 0 1 0 -- -- -- 0 0 Set 0 1 1 Reset 1 1 1 8-Bypass 1 1 1 Outputs Decade Out Q1 thru Q24 0 0 0 Counter is in three 8 stage sections in parallel mode. First "1" to "0" transition of clock. Comments All 24 stages are in Reset mode. 1 1 1 255 "1" to "0" transitions are clocked in the counter. 1 0 1 0 1 0 1 1 The 255 "1" to "0" transition. Counter converted back to 24 stages in series mode. Set and Reset must be connected together and simultaneously go from "1" to "0". In1 Switches to a "1". Counter Ripples from an all "1" state to an all "0" state. 1 0 0 0 0 0 0 0 1 0 MC14536B 8 MOTOROLA CMOS LOGIC DATA +V 16 6 9 8-BYPASS VDD OUT 1 4 A 10 B 11 C 12 2 14 15 PULSE GEN. PULSE GEN. CLOCK 1 7 3 D RESET OSC INH MONO-IN SET CLOCK INH IN1 VSS 8 OUT 2 5 DECODE OUT 13 IN1 SET CLOCK INH DECODE OUT POWER UP NOTE: When power is first applied to the device, Decode Out can be either at a high or low state. On the rising edge of a Set pulse the output goes high if initially at a low state. The output remains high if initially at a high state. Because Clock Inh is held high, the clock source on the input pin has no effect on the output. Once Clock Inh is taken low, the output goes low on the first negative clock transition. The output returns high depending on the 8-Bypass, A, B, C, and D inputs, and the clock input period. A 2n frequency division (where n = the number of stages selected from the truth table) is obtainable at Decode Out. A 20-divided output of IN1 can be obtained at OUT1 and OUT2. Figure 9. Time Interval Configuration Using an External Clock, Set, and Clock Inhibit Functions (Divide-by-2 Configured) MOTOROLA CMOS LOGIC DATA MC14536B 9 +V 6 RX 9 8-BYPASS 16 VDD OUT 1 4 A 10 B 11 C 12 D RESET SET CLOCK INH MONO-IN CLOCK INH IN1 VSS 8 2 1 7 15 14 3 PULSE GEN. OUT 2 5 CLOCK CX DECODE OUT 13 IN1 RESET *tw .00247 * RX * CX0.85 DECODE OUT *tw POWER UP NOTE: When Power is first applied to the device with the Reset input going high, Decode Out initializes low. Bringing the Reset input low enables the chip's internal counters. After Reset goes low, the 2n/2 negative transition of the clock input causes Decode Out to go high. Since the Mono-In input is being used, the output becomes monostable. The pulse width of the output is dependent on the external timing components. The second and all subsequent pulses occur at 2n x (the clock period) intervals where n = the number of stages selected from the truth table. tw in sec RX in k CX in pF Figure 10. Time Interval Configuration Using an External Clock, Reset, and Output Monostable to Achieve a Pulse Output (Divide-by-4 Configured) MC14536B 10 MOTOROLA CMOS LOGIC DATA +V RS 16 6 8-BYPASS VDD OUT 1 4 C 9 A 10 B 11 C 12 PULSE GEN. 2 14 15 1 7 3 D RESET SET CLOCK INH MONO-IN CLOCK INH IN1 VSS 8 DECODE OUT 13 OUT 2 5 RTC RESET OUT 1 OUT 2 fosc DECODE OUT POWER UP tw 1 ^ 2.3 Rtc C Rs Rtc F = Hz R = Ohms C = FARADS NOTE: This circuit is designed to use the on-chip oscillation function. The oscillator frequency is determined by the external R and C components. When power is first applied to the device, Decode Out initializes to a high state. Because this output is tied directly to the Osc-Inh input, the oscillator is disabled. This puts the device in a low-current standby condition. The rising edge of the Reset pulse will cause the output to go low. This in turn causes Osc-Inh to go low. However, while Reset is high, the oscillator is still disabled (i.e.: standy condition). After Reset goes low, the output remains low for 2n/2 of the oscillator's period. After the part times out, the output again goes high. Figure 11. Time Interval Configuration Using On-Chip RC Oscillator and Reset Input to Initiate Time Interval (Divide-by-2 Configured) MOTOROLA CMOS LOGIC DATA MC14536B 11 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE V -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 -B- 1 8 C L -T- SEATING PLANE N E F D G 16 PL K M J 16 PL 0.25 (0.010) M M TB S 0.25 (0.010) TA S P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 B 1 8 F S C L -T- H G D 16 PL SEATING PLANE K J TA M M 0.25 (0.010) M MC14536B 12 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS DW SUFFIX PLASTIC SOIC PACKAGE CASE 751G-02 ISSUE A -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 -B- 1 8 8X P 0.010 (0.25) M B M 16X D M J TA S 0.010 (0.25) B S F R X 45 _ C -T- 14X DIM A B C D F G J K M P R G K SEATING PLANE M Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MOTOROLA CMOS LOGIC DATA *MC14536B/D* MC14536B MC14536B/D 13 |
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